Quantinuum Systems

Subscription users can access the following targets:

• Quantinuum hardware

• Quantinuum emulators

• Machine-specific syntax checkers

Available targets accessible by end users. There are noisy and noiseless emulators hosted in Nexus. In addition, Quantinuum provides server-side emulators, syntax checkers and quantum computers, also accessible via Nexus.

Quantum Computers

Trapped ion quantum computers are available to users utilizing the System Model H2 and System Model H1 generation of quantum computers, powered by Honeywell. The qubit layouts on both System Models H2 and H1 are not static. Rather, any two qubits can be be transported into one of four or more parallel gate zones to allow all-to-all connectivity. The System Model H1 architecture consists of a linear trap [1]. The System Model H2 architcture is a racetrack shape [2]. The base trap architecture for both hardware generations is known as a Quantum Charge-Coupled Device (QCCD).

Individual machines that use the System Model H2 generation of ion traps are designated by the H2-X nomenclature while machines using the System Model H1 generation of ion traps are designated by the H1-X nomenclature. All devices under the H2-X or H1-X nomenclature use the same ion trap design, but at times may have a different number of parallel gate zones, maximum available qubits, and specific performance metrics. At all times, the performance of the quantum computers will have errors not exceeding the maximum errors listed in the Product Data Sheets.

System Model H1 Product Data Sheet

../../data_sheets/Quantinuum%20H1%20Product%20Data%20Sheet.pdf

System Model H2 Product Data Sheet

../../data_sheets/Quantinuum%20H2%20Product%20Data%20Sheet.pdf

Emulators

To support quantum algorithm development and design, emulators are available that model each machine’s specific ion transport and error rates. The emulators operate on a physical model as well as include a detailed error model of each Quantinuum quantum computer. In addition, options are provided to the user to experiment with the noise parameters of the emulator. The emulator user guide provides more information on operation and noise model capability.

Syntax Checkers

The syntax checkers are provided to check program syntax and are specific to each device. Before submitting quantum circuits to the Quantinuum hardware or emulators, use of a syntax checker is highly recommended. Jobs submitted to the Quantinuum hardware are in QIR (Quantum Intermediate Representation) format. The syntax checker enables checking of the code to ensure it will run before being submitted to the hardware or emulators. Access to a syntax checker corresponds to the machines available in a user’s subscription.

If the code compiles, the syntax checker will return a completed status, the cost of the circuit in Hardware Quantum Credits (HQCs), and results of all (0, 0, ..., 0). Submission to the syntax checker does not incur a HQC cost. If the code does not compile, the syntax checker will return a failed status and give the error returned.

API Interface

Direct communication with Quantinuum end points occurs via API endpoints based on the Quantum Intermediate Representation (QIR) or OpenQASM 2.0. The documentation on this website details examples in pytket and qnexus[3].

References

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[1]

J. M. Pino, J. M. Dreiling, C. Figgatt, J. P. Gaebler, S. A. Moses, M. S. Allman, C. H. Baldwin, M. Foss-Feig, D. Hayes, K. Mayer, C. Ryan-Anderson, and B. Neyenhuis. Demonstration of the trapped-ion quantum ccd computer architecture. Nature, 592(7853):209–213, April 2021. URL: http://dx.doi.org/10.1038/s41586-021-03318-4, doi:10.1038/s41586-021-03318-4.

[2]

S. A. Moses, C. H. Baldwin, M. S. Allman, R. Ancona, L. Ascarrunz, C. Barnes, J. Bartolotta, B. Bjork, P. Blanchard, M. Bohn, J. G. Bohnet, N. C. Brown, N. Q. Burdick, W. C. Burton, S. L. Campbell, J. P. Campora, C. Carron, J. Chambers, J. W. Chan, Y. H. Chen, A. Chernoguzov, E. Chertkov, J. Colina, J. P. Curtis, R. Daniel, M. DeCross, D. Deen, C. Delaney, J. M. Dreiling, C. T. Ertsgaard, J. Esposito, B. Estey, M. Fabrikant, C. Figgatt, C. Foltz, M. Foss-Feig, D. Francois, J. P. Gaebler, T. M. Gatterman, C. N. Gilbreth, J. Giles, E. Glynn, A. Hall, A. M. Hankin, A. Hansen, D. Hayes, B. Higashi, I. M. Hoffman, B. Horning, J. J. Hout, R. Jacobs, J. Johansen, L. Jones, J. Karcz, T. Klein, P. Lauria, P. Lee, D. Liefer, S. T. Lu, D. Lucchetti, C. Lytle, A. Malm, M. Matheny, B. Mathewson, K. Mayer, D. B. Miller, M. Mills, B. Neyenhuis, L. Nugent, S. Olson, J. Parks, G. N. Price, Z. Price, M. Pugh, A. Ransford, A. P. Reed, C. Roman, M. Rowe, C. Ryan-Anderson, S. Sanders, J. Sedlacek, P. Shevchuk, P. Siegfried, T. Skripka, B. Spaun, R. T. Sprenkle, R. P. Stutz, M. Swallows, R. I. Tobey, A. Tran, T. Tran, E. Vogt, C. Volin, J. Walker, A. M. Zolot, and J. M. Pino. A race-track trapped-ion quantum processor. Phys. Rev. X, 13:041052, Dec 2023. URL: https://link.aps.org/doi/10.1103/PhysRevX.13.041052, doi:10.1103/PhysRevX.13.041052.

[3]

Seyon Sivarajah, Silas Dilkes, Alexander Cowtan, Will Simmons, Alec Edgington, and Ross Duncan. T|ket⟩: a retargetable compiler for nisq devices. Quantum Science and Technology, 6(1):014003, November 2020. URL: http://dx.doi.org/10.1088/2058-9565/ab8e92, doi:10.1088/2058-9565/ab8e92.